Field of the Invention
This invention relates to a semiconductor integrated circuit device such as a memory, a photoelectric converting device, a signal processing device, etc. Such a device is with various electronic instruments, particularly with a semiconductor device having a specific feature in its electrode structure and a method for preparing the same.
Related Background Art
To describe the prior art, as an example, a vertical PNP (hereinafter abbreviated as V-PNP) transistor which has been used in recent years as a functional device for highly integrated semiconductor device may be mentioned, such as one having the structure shown in FIG. 1. In FIG. 1, the reference numeral 1 is a P-type silicon substrate. On the P-type silicon substrate 1 is formed an N.sup.+ buried layer 2, and on the N.sup.+ buried layer 2 is formed a collector region 5 comprising a P.sup.+ buried layer 3 and a P.sup.- well layer 4. Within the P.sup.- well layer 4 of the collector region 5 is formed an N.sup.- well layer 6, and further within the N.sup.- well layer 6 are formed a P.sup.+ layer 7 and an N.sup.+ layer 8 made apart from each other. Within the P.sup.- well layer 4 of the collector region 5 is formed a P.sup.+ layer 9 apart from the N.sup.- well layer 6. And, on the P.sup.+ layer 7, the N.sup.+ layer 8 within the N.sup.- well layer 6 and the P.sup.+ layer 9 within the P.sup.- well layer 4 are respectively formed an emitter electrode 10, a base electrode 11 and a collector electrode 12.
Around the collector region 5 as mentioned above, an N.sup.- epitaxial layer 13 is formed.
In the V-PNP transistor with such a structure, when the transistor actuation enters a saturation region (stage), leakage current may appear from the collector region 5 through the N-epitaxial layer 13 into the P-type silicon substrate 1, thereby forming a parasitic PNP transistor. For this reason, as shown in FIG. 2, there has been also known a transistor which has been made to have a constitution having a deep N.sup.+ layer 14 in contact with the N.sup.+ layer 2 and surrounding the collector region 5 formed within the N.sup.- epitaxial layer 13, and further in which the emitter grounding current amplification .beta. of the parasitic PNP transistor is reduced by biasing to the maximum potential. Thus, the leakage current to the P-type silicon substrate 1 can be reduced. The guard ring electrode 15 of the transistor is taken out from the N.sup.+ buried layer 2 through the N.sup.+ layer 14.
However, in the transistor of the type shown in FIG. 1 and FIG. 2, the current from the emitter electrode 10 flows into the P.sup.- well layer of the collector region 5 and the P.sup.+ buried layer 3, wherefrom it is taken out through the P.sup.+ layer 9 on the transistor surface at the collector electrode 12, and therefore the resistance of the P.sup.- well layer 4 becomes larger. Thus involving the drawback that the collector series resistance becomes larger as a whole. Further, when the collector series resistance becomes larger, the emitter grounding current amplification .beta. of a large current region becomes lower. While when the collector region 5 is larger, there will occur an inconvenience that the device size becomes larger.
In the transistor shown in FIG. 2, because the N.sup.+ layer 14 is required to be provided within the N.sup.- (epitaxial) layer 13 around the collector region 5, the margins of the collector region 5 and the device separation region 16 are required to be sufficiently large due to the influence of the lateral spreading of the diffusion layer, and therefore the device size also becomes larger in such a case. However, the junction capacity with the N.sup.+ layer 14 of the collector region 5 will be increased.
The technical task as described above is marked in the V-PNP transistor, and also in other functional devices, there is main electrode region (buried collector, buried base, buried emitter, buried source, buried drain, buried gate, etc.) within semiconductor substrate, and it is applicable similarly if a region for connecting electrically said electrode region to the electrode wiring on the substrate surface is required.